1. Field of the Invention
This invention relates generally to packaging for integrated circuits and, in particular, is directed to the fabrication of silicon-based chip carriers.
2. Description of Related Art
Integrated circuits are typically packaged in individual packages or carriers with the electrical interconnections between the packages provided by printed circuit boards. To improve circuit speed, manufacturers of electronic devices and, more importantly makers of high speed digital computers, strive to increase the density of both integrated circuits and circuit boards. As the active components of a circuit are brought physically closer together, the inherent delay associated with the transmission of electrical signals over interconnect lines is minimized. One major concern associated with the close physical placement of circuits, however, is the buildup of heat in a localized area. Another major concern is the level of cross-talk between the signal traces connecting such circuits, which can also limit the proximity of the circuits.
Chip carriers for individual high density integrated circuits are typically fabricated using a variety of substrates onto which metallized traces are placed to provide electrical connections from the periphery of the substrate to the integrated circuit packaged within. These traces are typically manufactured using printed circuit board technology and methods of miniaturizing that technology. Such techniques, however, result in carriers which consume large areas and which require longer connection lines between integrated circuits. The longer connection lines can ultimately slow the processing speed of machines using such carriers.
The need to provide increasing numbers of connections in a given area has resulted in the use of thin-film technology to bring traces from the integrated circuit to pins on the carrier. One technique is described in the co-pending and commonly assigned U.S. patent application Ser. No. 506,729, filed Apr. 9, 1990 by Steitz et al., entitled "METHOD OF FABRICATING METALLIZED CHIP CARRIERS FROM WAFER-SHAPED SUBSTRATES", which is incorporated herein by reference. That application, which is not prior art to the present invention, describes wafer-shaped substrates and thin-film manufacturing techniques for creating high density traces on chip carriers, with the carriers formed in the substrate prior to, or subsequent to, the formation of the traces. This technique attempts to further increase packing density of circuits.
Another attempt to increase packing density in circuits is wafer-scale integration. In this approach, the entire silicon wafer is fabricated using integrated circuit processing techniques to create a single, extremely dense circuit. These attempts have typically failed, however, due to the low overall yield of the processing technology. The low-yield resulted from the dependence of the overall yield on the individual yield rates of the low-yield devices placed within the single substrate.